As a designer or verification engineer, you’re fighting the effects of electrostatic discharge (ESD) in your integrated circuit (IC) designs all the time. ESD is one of those frustrating issues that ...

ICs subjected to electrostatic discharge (ESD) stress have distinct failure signatures. High currents can melt different regions of the semiconductor structure (ESD-HBM, or human body model), while ...

Advanced CMOS process technologies enable IC designers to deliver higher performing devices, but also increase the need for extra board-level ESD protection to ensure the reliability of the end ...

I was asked to help out a co-worker, “Joe”, a less-experienced engineer, with an ESD problem. Highly appropriate, after all, I had five whole years of work under my belt. The product was only a ...