EDN

Sequential clock gating maximizes power savings at IP level

Power Management is one of the major chip design challenges amongst all the dimensions of the design cycle. It poses problems for packaging, portability, & reliability (PPR), e.g.,“high system cost of ...
Nature

Liquid-based gating mechanism with tunable multiphase selectivity and antifouling behaviour

Figure 1: Hypothesis for gating a pore by liquid reconfiguration. Figure 2: Design and rational tuning of gating systems with differentially controlled gas and liquid transport. Figure 3: Sorting of ...
Electronic Design

Gate Drivers Help Power-System Designers Meet Requirements

Efficiency is the name of the game in power-system design, driven by the need to better leverage available energy and deliver more power from a smaller package. Except in some specialized or extremely ...
EDN

Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

SAN JOSE, Calif., May 3 /PRNewswire/ — Xilinx (Nasdaq: XLNX) today introduced the ISE® Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity ...