EDN

Dual PLL Spread Spectrum Clock Generator

The AD9577 provides a multioutput clock generator function along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on ...
Business Wire

Codasip looks to Silicon Creations’ PLL to drive RSIC-V Automotive Safety-Critical Core

ATLANTA--(BUSINESS WIRE)--Silicon Creations, a leading provider of high-performance analog and mixed-signal intellectual property (IP) today announced that its low-area integer PLL has been ...
Design-Reuse

General Purpose Integer Hybrid PLL, CLN28HPC/HPC+, 80MHz - 8000MHz

Kamaten Integer-N Hybrid (Analog with Digital Aid) PLL generates clock signals within broad frequency range. Division coefficients of the built-in inp ...
EDN

PLL design kit features timing models, GDSII physical views

A new design kit enables system-on-chip (SoC) developers to efficiently incorporate clocking IP into their designs with full support for layout, simulation, and timing closure. Perceptia Devices, an ...