EDN

IC static timing tool aids predictability

NanoTime is a next-generation transistor-level static timing analysis solution that provides concurrent timing and signal integrity analysis for ASIC designs. Its performance and capacity allow ...
Semiconductor Engineering

Closing The Post-Silicon Timing Analysis Gap

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...
EDN

Static timing analysis taken to RT level

San Mateo, Calif. – InTime Software Inc. will unveil a register-transfer-level timing tool this week intended to help IC designers develop timing-accurate RTL code before they move to synthesis, ...
Electronic Design

Timing Checks Go Full Chip

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...
Semiconductor Engineering

What Happened To Statistical Static Timing Analysis?

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).