SAN MATEO, Calif. — Sequence Design Inc. has introduced a static timing analysis tool that accounts for inductance delay and IR drop in ASICs and system-on-chip designs. In addition, the company has ...
SAN JOSE, Calif. — FPGA floorplanning startup Hier Design is introducing a new static timing tool add-on for its PlanAhead FPGA floorplanner, as well as new capabilities for a new version of PlanAhead ...
Magma's Tekton static timing analyzer is a next-generation tool built to handle the exploding number of STA scenarios required in modern SoC design. Static timing analysis (STA) is used throughout ...
Deftly optimizing ASIC critical paths, this tool rides atop existing cell-based flows to improve timing while leaving physical design largely undisturbed. Timing closure for ASIC design has always ...
SAN JOSE, Calif. -- May 20, 2013 -- In a move to ease and speed the development of complex ICs, Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced the Tempusâ„¢ Timing Signoff Solution, a ...
Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is ...
Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).
Synopsys is claiming a 5-10x speed-up and 5-10x capacity increase for static timing analysis (STA), with no loss of accuracy. The enhancement comes from a tool called HyperScale within the 2010.06 ...
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